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| IRF9620 Data Sheet July 1999 File Number 2283.2 3.5A, 200V, 1.500 Ohm, P-Channel Power MOSFET This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17502. Features * 3.5A, 200V * rDS(ON) = 1.500 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Symbol D Ordering Information PART NUMBER IRF9620 PACKAGE TO-220AB BRAND IRF9620 G S NOTE: When ordering, use the entire part number. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-21 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF9620 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF9620 -200 -200 -3.5 -2 -14 20 40 0.32 290 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw on Tab To Center of Die Measured From the Drain Lead, 6mm (0.25in) from Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D LD TEST CONDITIONS ID = -250A, VGS = 0V, (Figure 10) VGS = VDS, ID = -250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC =125oC VDS > ID(ON) x rDS(ON)MAX, VGS = -10V VGS = 20V ID = -1.5A, VGS = -10V, (Figures 8, 9) VDS > ID(ON) x rDS(ON)MAX, ID = -1.5A, (Figure 12) VDD = 0.5 x Rated BVDSS, ID -3.5A, RG = 50, RL = 26, for BVDSS = 200V RL = 20 for BVDSS = 150V (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = -10V, ID = -3.5A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VDS = -25V, VGS = 0V, f = 1MHz, (Figure 11) MIN -200 -2 -3.5 1 - TYP 1.000 1.8 30 50 80 50 16 9 7 350 100 30 3.5 MAX -4 -25 -250 100 1.500 50 100 120 75 22 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance - 4.5 - nH Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad G LS S 7.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Typical Socket Mount - - 3.12 80 oC/W oC/W 4-22 IRF9620 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX -3.5 -14 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TC = 25oC, ISD = -3.5A, VGS = 0V (Figure 13) TJ = 150oC, ISD = -3.5A, dISD/dt = 100A/s TJ = 150oC, ISD = -3.5A, dISD/dt = 100A/s - 300 1.9 -1.5 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 35.5mH, RG = 25, peak IAS = 3.5A (Figures 15, 16). Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified -5 0.8 0.6 0.4 0.2 0 ID, DRAIN CURRENT (A) -4 -3 -2 -1 0 0 50 100 150 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 ZJC, NORMALIZED THERMAL IMPEDANCE 0.2 0.1 0.1 PDM 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 1 10 t1 , RECTANGULAR PULSE DURATION (s) 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-23 IRF9620 Typical Performance Curves -100 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) -10 10s 100s Unless Otherwise Specified (Continued) -5 VGS = -10V VGS = -8V VGS = -9V VGS = -7V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -6V -3 1ms -1 TC = 25oC TJ = MAX RATED SINGLE PULSE -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) 10ms 100ms DC -1000 -2 VGS = -5V -1 VGS = -4V 0 0 -10 -20 -30 -40 -50 -0.1 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS -5 ID(ON), ON STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) -4 VGS = -7V -5 VDS I D(ON) x rDS(ON) MAX VGS = -8V -3 VGS = -9V VGS = -10V -2 VGS = -6V VGS = -5V -1 VGS = -4V 0 0 -4 -2 -3 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) -5 PULSE DURATION = 80s -4 DUTY CYCLE = 0.5% MAX TJ = 125oC -3 TJ = 25oC TJ = -55oC -2 -1 0 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -10 FIGURE 6. SATURATION CHARACTERISTICS 5 PULSE DURATION = 2s 4 ON RESISTANCE () NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE 2.5 FIGURE 7. TRANSFER CHARACTERISTICS VGS = -10V, ID = -1.5A PULSE DURATION = 80s 2.0 DUTY CYCLE = 0.5% MAX 3 VGS = -10V 2 1.5 1.0 1 VGS = - 20V 0.5 0 0 4 12 8 ID, DRAIN CURRENT (A) 16 20 0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-24 IRF9620 Typical Performance Curves 1.25 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 400 C, CAPACITANCE (pF) Unless Otherwise Specified (Continued) 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS 1.05 300 0.95 200 COSS CRSS 0.85 100 0.75 -40 0 0 40 80 120 160 0 TJ , JUNCTION TEMPERATURE (oC) 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4.0 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3.2 TJ = -55oC 2.4 TJ = 25oC TJ = 125oC -100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -10 TJ = 150oC 1.6 -1.0 TJ = 25oC 0.8 0 0 -1 -2 -3 -4 -5 I D , DRAIN CURRENT (A) -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 ID = -3.5A VGS, GATE TO SOURCE (V) -5 VDS = -60V VDS = -40V -10 VDS = -100V 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-25 IRF9620 Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr 0 RL 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR -VDS (ISOLATED SUPPLY) 0 DUT VDS 12V BATTERY 0.2F 50k 0.3F Qgs D G DUT VDD Qgd Qg(TOT) VGS 0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 IG(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 4-26 IRF9620 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-27 |
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